Current limiting protection circuit

Abstract

A current-limit circuit comprising a control transistor coupled to a power transistor in a current mirror configuration. A switch transistor is operatively coupled between the output of the power transistor and the control transistor to selectively activate the control transistor in response to an over current condition detected by a defect transistor. Current drawn through the power transistor in the over current condition is limited by the control transistor which is powered from the gate of the power transistor. The power and detect transistors are integrated on a semi-conductor substrate of a first conductivity type defining first and second surfaces. An array of adjacent transistor body regions of a second conductivity type provided adjacent said first surface with gate electrodes extending between adjacent body regions and insulated therefrom by a gate insulator layer. Transistor source regions of said first conductivity type are provided in said body regions adjacent said gate electrodes. Transistor source electrode material overlies the gate electrodes and is insulated therefrom by an insulation layer, the source electrode material contacting the source/body regions between adjacent gate electrodes. The source electrode layer is patterned to define first and second adjacent regions providing source contact to the power and detect transistors respectively. Electrodes of the power transistor are isolated from adjacent gate electrodes of the detect transistor by intervening body regions devoid of source regions adjacent one or both of said adjacent gate electrodes.