The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2004
Filed:
Sep. 10, 2002
Sachin Chopra, Cupertino, CA (US);
Yu-Yen Mo, San Jose, CA (US);
Shyam Sundar, Sunnyvale, CA (US);
Peter F. Lai, San Jose, CA (US);
Kong-Fai Woo, San Jose, CA (US);
Venkat Podduturi, San Jose, CA (US);
Vishal Chopra, Cupertino, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.