The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2004
Filed:
May. 22, 2002
Applicant:
Inventors:
Viswanathan Lakshmanan, Westminster, CO (US);
Michael Josephides, Louisville, CO (US);
Tom R. O'Brien, Ft. Collins, CO (US);
David A. Morgan, Ft. Collins, CO (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.
Quick Actions:
Lakshmanan, Viswanathan. (2004). Chip design method for designing integrated circuit chips with embedded memories (U.S. Patent No. 6775811). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6775811
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile