The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2004

Filed:

Sep. 25, 2002
Applicant:
Inventors:

Kozo Ishida, Tokyo, JP;

Hideki Yonetani, Tokyo, JP;

Takeshi Ohgami, Tokyo, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

Power to operates memory bank of DRAM stably is supplied with reduced power consumption. A semiconductor storage unit includes multiple arrays forming memory banks on a substrate, first and second power supplies. Multiple arrays are arranged like a matrix and surround the central region of the substrate. Each memory bank consists of two of the multiple arrays. Each first power supply supplies driving power to a peripheral circuit which drives each multiple array. Second power supplies are arranged at four corners of the central region, each supply provides access power to word lines which access the multiple arrays. The first power supplies are mounted to a central and the opposite side for predetermined arrays, serve as a main and an auxiliary power supply to provide main and auxiliary power (smaller than the main power), and provide distantly arranged two of the multiple arrays forming a memory bank with power.


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