The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2004
Filed:
Jan. 15, 2003
Kazutaka Nogami, Tokyo, JP;
Thine Electronics Inc., Tokyo, JP;
Abstract
In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit. The semiconductor integrated circuit includes a first circuit for activating a first phase difference signal corresponding to a phase difference between a first clock signal and a second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal, a second circuit for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, a third circuit for combining the first phase difference signal and the first pulse signal, and a fourth circuit for combining the second phase difference signal and the second pulse signal.