The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2004
Filed:
Apr. 09, 2001
Kenichi Ishihara, Yokosuka, JP;
Kenichi Shiraishi, Yokohama, JP;
Soichi Shinjo, Machida, JP;
Akihiro Horii, Zama, JP;
Other;
Abstract
A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter ( ), a carrier of the counter ( ) stores outputs from a PN data generator ( ) in a shift register ( ), outputs from a PN comparison circuit ( ) when stored data agree with count values of the counter ( ) are recognized as error pulses, a bit selector ( ) randomly selects, on receiving error pulses and based on outputs from a PN data generator ( ), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit ( ) for outputting to thereby add errors.