Clock control circuit for rambus dram

Abstract

A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command. Our circuit includes: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with a device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with a device address value of a COLX packet is enabled, and when the command is a read or current control command; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting a control signal for maintaining the clock enable signal to the signal generating unit in the read or current control command; and an output signal control unit for outputting a control signal for controlling generation of the clock enable signal to the signal generating unit, when the command is not the read or current control command.