The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2004

Filed:

Dec. 19, 2000
Applicant:
Inventors:

Ian W. Jones, Palo Alto, CA (US);

Josephus C. Ebergen, San Francisco, CA (US);

Assignee:

Sun Microsystems, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 ; G06F 3/06 ; G06F 5/00 ;
U.S. Cl.
CPC ...
G06F 3/00 ; G06F 3/06 ; G06F 5/00 ;
Abstract

Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to “n” stages of the FIFO and configured to output a partial fullness indicator signal based on the full/empty states of the stages coupled to the m-out-of-n detector. The m-out-of-n detector may be configured to output the partial fullness indicator signal in a first state when “m” stages coupled to the m-out-of-n detector are full, and to output the partial fullness indicator signal in a second state when “m” stages coupled to the m-out-of-n detector are empty. The number of full stages of the FIFO lies in a first range when the m-out-of-n detector outputs the signal in the first state, and in a second range when the m-out-of-n detector outputs the signal in the second state. The bounds for the ranges may be determined based on factors such as the input and output rate characteristics of the FIFO. The m-out-of-n detector may be used to indicate partial fullness levels for various FIFOs including linear flow-through FIFOs, serial-concurrent-serial (SCS) FIFOs, and the like.


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