The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2004
Filed:
Feb. 06, 2002
Applicant:
Inventors:
Matthew S. Von Thun, Colorado Springs, CO (US);
Brian E. Burdick, Colorado Springs, CO (US);
Edson W. Porter, Colorado Springs, CO (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/7687 ;
U.S. Cl.
CPC ...
H03K 1/7687 ;
Abstract
An apparatus comprising a device and a resistor. The device generally comprises (i) a gate configured to receive an input voltage, (ii) a drain coupled to a first supply voltage, and (iii) a source coupled to an output. The resistive element is generally coupled between the source and a second supply voltage. The apparatus generally provides voltage tolerance between the input voltage and the output.
Von Thun, Matthew. (2004). Five volt tolerant and fail safe input scheme using source follower configuration (U.S. Patent No. 6771113). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6771113
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile