The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2004
Filed:
Feb. 24, 2000
Applicant:
Inventors:
Tsutomu Ishikawa, Ohta, JP;
Hiroshi Kojima, Gunma-ken, JP;
Assignee:
Sanyo Electric Co., Inc., , JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/7687 ;
U.S. Cl.
CPC ...
H03K 1/7687 ;
Abstract
An integrated semiconductor device is provided that has pads with less input signal attenuation. When J-FET ( ) is driven by an input signal, the current passing through it varies. The parasitic capacitance ( ) is charged or discharged by the input/output signal of the buffer circuit ( ) following the varying current. Thus, since the voltage across the parasitic capacitance ( ) varies in phase and at the same level, the parasitic capacitance ( ) can be ignored. This effect allows attenuation of an input signal due to the parasitic capacitance ( ) to be prevented.