The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2004
Filed:
Aug. 31, 1998
Shafy Eltoukhy, Los Gatos, CA (US);
Lightspeed Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A system and method in accordance with the invention minimizes the redesign burden in tuning and/or customizing PLLs on ICs. Variable resistors are placed in the PLL in places that facilitate tuning. The variable resistors are formed with a set of at least three contacts, where each contact is in electrical communication with a resistive area. A metal layer is used to form leads to the resistive area, where each lead is formed to be in electrical communication with only a selected subset of contacts from the set. In one embodiment, only the uppermost metal layer used in forming the IC is used to form the leads. Because the uppermost metal layer is utilized, the resistor value can be adjusted simply by selecting the subsets of contacts that are to be in electrical communication with the uppermost metal layer. In this manner, only one metal layer needs to be adjusted in tuning and/or customizing a PLL, rather than having to redesign and re-layout all metal layers and vias in the IC.