The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2004

Filed:

Oct. 21, 1999
Applicant:
Inventors:

Thomas F. Marinis, Haverhill, MA (US);

Jerome B. Sohn, Sudbury, MA (US);

Richard P. Tumminelli, Ashland, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/100 ; H01L 2/144 ; H01L 2/714 ;
U.S. Cl.
CPC ...
H01L 2/100 ; H01L 2/144 ; H01L 2/714 ;
Abstract

A micromechanical sensor is fabricated on a semiconductor wafer, and a control circuit is fabricated on another semiconductor wafer. A cavity is etched on the back side of the control circuit wafer, the cavity being formed such that the sensor on the other wafer fits within the cavity when the wafers are brought together in an adjoining relationship. Through-holes are etched through the back side of the control circuit wafer to allow access to electrical contact points, and a patterned layer of metal is deposited to form electrical interconnections between the electrical contact points and termination points on the back side of the wafer via the through-holes. The termination points are arranged such that electrical contacts of the sensor contact the termination points when the wafers are placed in the adjoining relationship. The wafers are then cleaned and bonded together in the adjoining relationship. In a typical process the wafers contain multiple sensors and control circuits, respectively, and thus the bonded wafers are diced to yield individual bonded sensor-circuit pairs. The bonded pairs are then packaged in an integrated-circuit package such as a leadless chip carrier in a known manner.


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