The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2004

Filed:

Oct. 30, 2002
Applicant:
Inventor:

Arun Ananth Aiyer, Fremont, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N 2/100 ;
U.S. Cl.
CPC ...
G01N 2/100 ;
Abstract

A wafer inspection apparatus having a stage with a support surface on which a wafer substrate may rest. The wafer stage is capable of moving the wafer in (x, y) or (r, &thgr;) mode to achieve complete wafer scan. Polarized light from a monochromatic source is directed towards the wafer surface . The state of polarization of the beam entering PBS is either s- or p- or circular depending on the exemplary embodiment of the invention. Alternatively, both s- and p-polarization components are simultaneously present with the optical frequency of one of them shifted by &Dgr;f with respect to the other. The reflected light is sensed by detector(s) or and . A processor in communication with the detector(s) can generate image of the wafer surface based on reflectance data from a plurality of points generated via wafer (r, &thgr;) scan. The polarizing beam splitters (PBS) and along with the turning mirrors through are configured such that every ray from the source that is directed toward PBS is propagated in two orthogonal planes of incidence. In another exemplary embodiments, two images of the wafer surface taken simultaneously with two counter propagating beams and processed to enhance defect signal while suppressing geometry generated background noise. Current invention also provides for normal illumination of the wafer surface along with off-axis illumination. Dark field inspection can also be implemented in anyone of the described exemplary embodiments by locating off-axis detectors . Other embodiments describe phase-image inspection of wafer surface for detecting those defects that are insensitive to dark field or bright field inspection using two phase images that are 180° apart in phase.


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