The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2004

Filed:

Jul. 10, 2002
Applicant:
Inventors:

Edward Colton Greene, Portola Valley, CA (US);

Patrick Matthew Hanrahan, Portola Valley, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/500 ;
U.S. Cl.
CPC ...
G06T 1/500 ;
Abstract

Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e.g., in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.


Find Patent Forward Citations

Greene, Edward. (2004). Method and apparatus for occlusion culling in graphics systems (U.S. Patent No. 6768487). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6768487

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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