The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2004

Filed:

Oct. 25, 2002
Applicant:
Inventors:

Clifford W. Meyers, Rancho Palos Verdes, CA (US);

Lloyd F. Linder, Agoura Hills, CA (US);

Kenneth A. Essenwanger, Walnut, CA (US);

Don C. Devendorf, Carlsbad, CA (US);

Erick M. Hirata, Torrance, CA (US);

William W. Cheng, Redondo Beach, CA (US);

Assignee:

Raytheon Company, Lexington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/36 ;
U.S. Cl.
CPC ...
H03M 1/36 ;
Abstract

An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) ( ) with a novel active offset method for comparators. The novel ADC architecture ( ) includes a first circuit ( ) for receiving an input signal; a second circuit ( ) for setting a predetermined number of thresholds using a predetermined number of preamplifiers ( ) with weighted unit current sources ( ) in each of the preamplifier outputs; and a third circuit ( ) for comparing the input to the thresholds. In the preferred embodiment, the ADC ( ) includes trimmable current sources ( ). The ADC ( ) of the present invention also includes an improved comparator circuit ( ). The novel comparator ( ) includes split load resistors, pairs R (active mode) and R and pairs R (active mode) and R , to increase the acquisition time and reduce the regeneration time constant, emitter follower buffers Q and Q on the latch pair transistors Q and Q to reduce the capacitive loading on the regeneration node, and cascode transistors Q and Q coupled to the load resistors to eliminate the output loading effects from the regeneration node. In the preferred embodiment, the invention also includes a novel DDS/DAC architecture ( ) with digitally trimmed unary currents and a novel sine lookup and decoder design which overcomes the conventional dynamic range limitations at high conversion rates.


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