The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2004
Filed:
Mar. 20, 2003
Tomohiro Kaneko, Kanagawa, JP;
Kazuo Tozawa, Kanagawa, JP;
NEC Electronics Corporation, Kanagawa, JP;
Abstract
A circuit is disclosed that can output signals from different circuit blocks at a common output terminal with a smaller number of transistors than conventional approaches. When a level shifter circuit receives a high voltage level at a control terminal ( ), a level shifter unit ( ) is placed in the operational state to provide an output signal from a low voltage system block, and a clocked inverter ( ) is placed in the non-operational state. When a level shifter circuit receives a low voltage level at a control terminal ( ), a clocked inverter ( ) is placed in the operational state to provide an output signal from a high voltage system block. At the same time, PMOS transistor ( ) can be turned on, resulting in PMOS transistors ( ) being turned off. Further, NMOS transistors ( and ) are turned off. This can result in an output impedance of a level shifter unit ( ) being set to a high impedance state. Thus, an output from a level shifter unit ( ) can have essentially no influence on an output signal of clocked inverter ( ).