The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2004
Filed:
Aug. 29, 2002
Applicant:
Inventors:
Palle Birk, Gistrup, DK;
Joern Soerensen, Aars, DK;
Assignee:
Analog Devices, Inc., Norwood, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 ;
U.S. Cl.
CPC ...
H03L 7/06 ;
Abstract
A PLL frequency multiplier is provided having a latency substantially equal to the wake-up time of the PLL. An operative clock signal is provided to a processor while the PLL is acquiring phase lock by ensuring that the clock signal does not contain frequencies above a target frequency of a PLL and below a predetermined threshold frequency. In particular, a frequency divider and a frequency detector are provided to prevent the frequency of the clock signal from operating outside the range defined by the threshold and target frequencies.