The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2004
Filed:
Jun. 04, 2003
James Anderson, Huntington Beach, CA (US);
Gershon Akerling, Culver City, CA (US);
Northrop Grumman Corporation, Los Angeles, CA (US);
Abstract
A packaged die ( ) for an integrated circuit ( ) that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit ( ) is still in a wafer format. A wafer substrate ( ) on which the integrated circuits ( ) have been fabricated is patterned and etched to form signal and ground vias ( ) through the substrate ( ). A back-side ground plane ( ) is deposited in contact with the ground vias ( ). A protective layer ( ) is formed on the top surface ( ) of the substrate ( ), and a protective layer ( ) is formed on the bottom surface ( ) of the substrate ( ), where the bottom protective layer ( ) fills in removed substrate material between the integrated circuits ( ). Vias ( ) are formed through the bottom protective layer ( ), and the wafer substrate ( ) is diced between the integrated circuits ( ).