The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2004
Filed:
Apr. 30, 2002
Homi E. Nariman, Austin, TX (US);
David E. Brown, Austin, TX (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilicon above the doped layer of polysilicon and performing an etching process on the undoped layer of polysilicon and the doped layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode. In further embodiments, the method comprises forming a layer of refractory metal above the gate electrode and performing at least one heating process to form a metal silicide region on the gate electrode structure. In another illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a first layer of polysilicon above the gate insulation layer, implanting a dopant material into the first layer of polysilicon to form a doped region having a dopant concentration level in the layer of polysilicon, forming a second layer of polysilicon above the doped region of the first layer of polysilicon, the second layer of polysilicon having a dopant concentration level that is less than the dopant concentration level of the doped region in the first layer of polysilircon, and performing an etching process on the second layer of polysilicon and the doped region in the first layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode.