The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2004
Filed:
Jul. 17, 2002
Suresh R. Puthucode, Bangalore, IN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The failure rate of an integrated circuit (IC) is quickly determined by analyzing the corresponding design. The IC is partitioned into multiple cells, with each cell typically containing a logic gate. A default input signal is assumed for each cell and the default failure in time (FIT) rates of the cells are computed. The default signal is selected based on pessimistic assumptions on overshoots. The IC is analyzed to determine the cells (“overshoot cells”) that would actually experience overshoots. Detailed analysis is performed on the overshoot cells to determine exact FIT rates. The failure rate of the IC is determined based on the exact FIT rates for the overshoot cells and the default FIT rates for the remaining cells.