The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 20, 2004

Filed:

Mar. 11, 2002
Applicant:
Inventors:

Andrew R. Adams, Stanmore, AU;

Stephen C. Avery, Kellyville, AU;

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 ;
U.S. Cl.
CPC ...
H03D 3/24 ;
Abstract

A phase locked loop (PLL) frequency synthesizer includes a voltage controlled oscillator (VCO) to provide a VCO frequency signal, a frequency offset circuit including a mixer accepting the VCO frequency signal and a signal from a second oscillator to produce a shifted-frequency signal having a frequency significantly lower than the VCO output frequency, a programmable divider accepting the shifted-frequency signal and dividing the frequency of the shifted-frequency signal by a settable amount, a phase detector to compare the phase of the output of the programmable divider to that of a reference oscillator and produce a phase difference signal; and a loop filter to filter a function of the phase difference to produce a control input to the VCO. The offset circuit shifts down the frequency without increasing the divide ratio of the loop as would a prescaler achieving the same frequency conversion as the frequency offset circuit.


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