The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2004
Filed:
Sep. 13, 2000
Applicant:
Inventor:
Jong-Hoon Oh, Fremont, CA (US);
Assignee:
G-Link Technology, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 ;
U.S. Cl.
CPC ...
H03L 7/06 ;
Abstract
A significantly more efficient implementation of a DLL for systems using two separate clock signals, whereby a single DLL circuit is used to provide for locking of both clock signals. According to the present invention, the input to the DLL is controlled such that it responds to edges of both clock signals. The present invention provides a circuit receiving a first periodic signal CLK and a second periodic signal CLK , there being a phase difference between CLK and CLK , the circuit including a delay-locked loop (DLL) having one delay path, wherein the same delay path provides delay tuning for both CLK and CLK