Method for reducing a parasitic capacitance of a semiconductive memory cell using metal mask for sidewall formation

Abstract

The present invention provides a method for reducing loading capacitance. The inventive method includes the steps of: forming a plurality of patterns on a substrate, wherein the patterns are formed by stacking and patterning a first conductive layer, a silicon nitride mask layer and a metal mask layer on the substrate; depositing a first silicon oxide layer along the profile containing the patterns; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer, wherein the metal mask layer prevents losses of the silicon nitride mask layer; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole that is partially expanded to the top portion of the patterns; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer.