Slicer arrangement

Abstract

A circuit arrangement including means for determining a slicer level from incoming signal levels for slicing the incoming signal levels on the basis of the slicer level thus determined, includes a first and a second register circuit, which register circuits are connected to an output of a discriminator circuit. The discriminator circuit compares an incoming signal level with a set discrimination level and is adapted to apply an incoming signal level to the first register circuit if the incoming signal level is higher than the set discrimination level and to apply and incoming signal level to the second register circuit if the incoming signal level is lower than the set termination level. The first and the second register circuit are adapted to determine a register value of a least two different incoming signal levels consecutively applied to the register circuit. The circuit supplies a signal having a level which is a value determine from register values determined by the first and second register circuit. The supplied signal represents both the set discrimination level and the slicer level.