The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2004

Filed:

Jul. 11, 2002
Applicant:
Inventors:

Yoshihiko Inoue, Chikushino, JP;

Hisashi Motomura, Fukuoka, JP;

Masashi Horiguchi, Koganei, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A semiconductor memory capable of reducing refresh cycle time, which includes normal memory cells provided at predetermined intersections of plural normal word lines and plural bit lines, and redundant memory cells of redundant word lines and the plural bit lines, a redundancy relief circuit evaluates whether each of an internal address signal for a memory operation and a refresh address signal corresponds to the address of a defective word line of the plural normal word lines. An address selecting circuit switches the defective word line to a redundant word line according to the evaluation result. The redundancy relief circuit then evaluates whether a refresh address added to the refresh address signal corresponds to a defective address, and during refresh, the address selecting circuit selects a normal or redundant word line according to the evaluation result in a preceding cycle.


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