The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2004

Filed:

Jan. 22, 2003
Applicant:
Inventors:

Nikola Subotic, Ann Arbor, MI (US);

Christopher Roussi, Kalamazoo, MI (US);

Joseph Burns, Ann Arbor, MI (US);

Assignee:

Altarum Institute, Ann Arbor, MI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 3/02 ; H01Q 3/12 ;
U.S. Cl.
CPC ...
H01Q 3/02 ; H01Q 3/12 ;
Abstract

An antenna pattern disposed on a three-dimensional object is used to optimize gain, beam pattern, polarization response, or other qualities despite or independently of physical orientation. In the preferred embodiment a fractal array is used on a polyhedron, though non-fractal and other self-replicating antenna patterns may be generated through the use of additional transformations and candidate geometric shapes to achieve patterns which are not only arbitrary in terms of wavelength/frequency, but also permit variable radiation patterns and variable polarization other desirable criteria. In addition to the use of variable scaling, geometric patterns, and the like, multiple structures may be placed within the same spatial footprint to permit reception over more bands. As an alternative to a fixed pattern with switches used to swap elements or change feed points, a reconfigurable multi-dimensional array may be used having an active area optimized to maximize reception for a desired frequency and/or direction. This aspect of the invention may exploit flat-panel technology, wherein, for example, a conductor array face on the object may be mapped to an addressable interconnect back plane to achieve a desired level of reconfigurability.


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