Built-in self test for speed and timing margin for a source synchronous io interface

Abstract

A built-in self test implementation for testing the speed and timing margins of the IO pins of a source synchronous IO interface (SSIO). The implementation preferably includes built-in self test logic including a pseudo-random pattern generator which is configured to generate input sequences. Buffers are connected to the IO pins, and the buffers are configured to receive the input sequences. The buffers are connected to multiple input signature registers, and the multiple input signature registers are configured to receive the input sequences from the pseudo-random pattern generator and generate signatures. Comparators are provided to compare the signatures to expected vector values and generate a pass/fail output signal. Preferably, at least one programmable delay cell is disposed between each buffer and the multiple input signature registers. The programmable delay cells provide that propagation delays can be set to perform timing margin tests.