The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2004

Filed:

Mar. 23, 2000
Applicant:
Inventors:

Akio Tajima, Tokyo, JP;

Hiroaki Takahashi, Tokyo, JP;

Soichiro Araki, Tokyo, JP;

Naoya Henmi, Tokyo, JP;

Yoshihiko Suemura, Tokyo, JP;

Yoshiharu Maeno, Tokyo, JP;

Seigo Takahashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 1/006 ;
U.S. Cl.
CPC ...
H04B 1/006 ;
Abstract

An optical receiving circuit is composed of a preamplifier circuit , an output differential amplifier and a mean value holding circuit . The optical receiving circuit is connected to a photodetector for receiving an input optical signal and outputting current. For the preamplifier circuit , a transimpedance type circuit may also be used. The preamplifier circuit comprises a feedback resistor and a resistor for detecting output voltage , the transimpedance gain is 55 dB &OHgr; and 3 dB bandwidth when the photodetector the capacity of which is 0.2 pF is connected to its output is 8 GHz. The output differential amplifier discriminates and regenerates data by regulating reference voltage Vref between the high level and the low level of the amplitude of an input signal. The mean value holding circuit includes a sample-hold circuit and capacity for holding the mean value of voltage output from the preamplifier circuit . As a CR time constant based upon the capacity and the resistor for detection is 1 ns., the mean value level of a received signal can be detected in approximately one byte of the data of 10 Gb/s. The sample-hold circuit samples the detected mean value level according to a sampling pulse from an external device and holds it. The output of the sample-hold circuit is used for the reference voltage of the differential amplifier


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