The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2004
Filed:
Mar. 16, 2000
Richard B. Merrill, Woodside, CA (US);
Richard M. Turner, Menlo Park, CA (US);
Milton B. Dong, Saratoga, CA (US);
Richard F. Lyon, Los Altos, CA (US);
Foveon, Inc., Santa Clara, CA (US);
Abstract
An integrated active pixel sensor array arranged in a plurality of rows and columns comprises a saturation level line coupled to a source of saturation level control voltage, a global current-summing node. A plurality of active pixel sensors is disposed in the array, each pixel sensor associated with one row and one column of the array and including a photodiode having a first terminal coupled to a first potential and a second terminal, a reset transistor having a first terminal coupled to the second terminal of the photodiode, a second terminal coupled to a reset reference potential that reverse biases the photodiode, and a control gate coupled to the reset line, a photocharge integration node coupled to the second terminal of the photodiode, the photocharge integration node comprising the gate of a first source-follower transistor, the first source-follower transistor having a drain, coupled to a first source-follower drain line, and a source, a circuit for generating a bias current at the source of the first source follower transistor, and an exposure transistor having a source coupled to the source of the first source-follower transistor, a drain coupled to the global current-summing node and a control gate coupled to the saturation level line.