The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2004
Filed:
Mar. 30, 2001
Eiji Yanagawa, Tenri, JP;
Akihiko Nakano, Nara, JP;
Toshinori Ohmi, Nara, JP;
Hironori Matsumoto, Nara, JP;
Tadao Takeda, Ebina, JP;
Hideyuki Unno, Ebina, JP;
Hiroshi Ban, Machida, JP;
Other;
Abstract
In the present semiconductor device, a chip with an LSI circuit is secured to a board (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.