The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6757788 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 29, 2004

Filed:

Aug. 30, 2001
Applicant:
Inventors:

Shinichi Kawamoto, Hachioji, JP;

Tatsuo Higuchi, Fuchu, JP;

Hiromitsu Maeda, Yokohama, JP;

Naoki Hamanaka, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/300 ;
U.S. Cl.
CPC ...
G06F 1/300 ;
Abstract

A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.


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Kawamoto, Shinichi. (2004). Cache coherent control system for network nodes allows cpu or i/o device to access target block without cache coherence control, if associated node has access right in an access right memory to target block (U.S. Patent No. 6757788). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6757788

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