The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2004
Filed:
Dec. 16, 2002
Harry A. Eaton, Columbia, MD (US);
The Johns Hopkins University, Baltimore, MD (US);
Abstract
A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a three-input OR-NAND as well as a static RAM bit cell. SEU immunity is obtained by constructing each logic element with a redundant set of inputs and using two copies of each such logic element to provide redundant outputs. The design of a logic element is such that when the redundant inputs agree (i.e., each has the same logic value), then the output of the logic element implements the logic function. However, when any pair of redundant inputs disagree, then the output of the logic element is disconnected(tri-state), which preserves the previous output value. SEU events only affect one of the logic elements in the pair, and this upset can not propagate through other logic elements because of the tri-state function.