The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2004

Filed:

May. 14, 2002
Applicant:
Inventor:

Yasunari Furuya, Nagano-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9003 ;
U.S. Cl.
CPC ...
H03K 1/9003 ;
Abstract

The clock edge detection circuit is equipped with a first delay circuit that delays a first clock signal and outputs a first delay clock signal, a second delay circuit that delays a second clock signal and outputs a second delay clock signal, a first retaining circuit that retains a level of the first delay clock signal at an edge of the second clock signal, a second retaining circuit that retains a level of the first clock signal at an edge of the second delay clock signal, and a logical circuit that outputs, based on the output signals of the first and second retaining circuits, a detection signal representing whether or not an edge of the first clock signal and an edge of the second clock signal are within a predetermined time range.


Find Patent Forward Citations

Furuya, Yasunari. (2004). Clock edge detection circuit (U.S. Patent No. 6756808). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6756808

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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