The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2004
Filed:
Dec. 07, 2000
Elana D. Granston, Sugar Land, TX (US);
Joseph Zbiciak, North Richland Hills, TX (US);
Alan S. Ward, Sugar Land, TX (US);
Eric J. Stotzer, Houston, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method for reducing a code size of a software pipelined loop, the software pipelined loop having a kernel and an epilog. The method includes first evaluating a stage of the epilog. This includes selecting a stage of the epilog to evaluate ( ) and evaluating an instruction in a reference stage. This includes identifying an instruction in the reference stage that is not present in the selected stage of the epilog ( ) and determining if the identified instruction can be speculated ( ). If the identified instruction can be speculated, such is noted. If the instruction cannot be speculated, it is determined whether the identified instruction can be predicated ( ). If the instruction can be predicated, it is marked as needing predication ( ). Next, it is determined if another instruction in the reference stage is not present in the selected stage of the epilog ( ). If there is, the instruction evaluation is repeated. If there is another stage of the epilog to evaluate, the evaluation is repeated ( ).