Programmable stabilization interval for internal stop grant state during which core logic is supplied with clocks and power to minimize stabilization delay

Abstract

An integrated circuit provides for changes to its core clock frequency and its core voltage using software programmable registers on the processor to store voltage ID (VID) values to specify core voltage, which are supplied to a voltage regulator and clock frequency control values, which are supplied to clock generation logic on the integrated circuit to specify core clocks. The integrated circuit generates an internal state in which its core clocks are stopped or slowed and during which core voltage and core frequency are adjusted. The processor also includes a timing mechanism that allows the new voltage and clock frequency to stabilize before resuming core operations. The timing mechanism may include a programmable count to specify the time to allow the new voltage and clock frequency to stabilize.