Providing data in response to a read command that maintains cache line alignment

Abstract

Efficient memory operation is provided by maintaining alignment with cache line boundaries in response to a read command. A prefetching scheme is used to limit the amount of operations needed to respond to a read command. In addition, the prefetch amount is initially adjusted where the starting address of the read request falls in between cache line boundaries. The adjusted read amount is determined based on the misaligned portion from the starting address of the read request to the nearest cache line boundary outside of the requested data block, such that the adjusted read amount ends on a cache line boundary. Subsequent read requests to the same data block will thereby begin at the last cache line boundary and end upon a subsequent cache line boundary by providing the pre-configured prefetch data amount corresponding to the requesting master device. Efficient bus utilization and memory controller operation efficiency is maximized by allowing the memory control to operate and respond to read requests in data amounts maintaining cache line alignment.