High speed trellis encoding for discrete multitone transceivers

Abstract

A three-stage four-dimensional encoding system and method for DMT-based transceivers includes a first stage where a parallel shifter shifts three bits of input data bits from a shadow register into a holding register. Next, a convolutional encoder generates encoded bits v , v , w and w , using the three bits in the holding register. The encoded bits w and w may be registered as w ′ and w ′ for later use. In the second stage, the encoded bits v and v are provided to the inputs of the parallel shifter for parallel parsing of bits for the first tone of a pair of tones of DMT and the number of bits needed for the first tone are parallel shifted to the holding register. The bits in the holding register are then mapped by a constellation mapper into a constellation point. In the third stage, the encoded bits w ′ and w ′ are provided to the inputs of the parallel shifter for parallel parsing of bits for the second tone of the pair of tones and the number of bits needed for the second tone are parallel shifted to the holding register. The bits in the holding register are then mapped by a constellation mapper into a constellation point.