The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2004
Filed:
Jul. 18, 2002
Thomas Janik, München, DE;
Sebastian Kuhne, Radebeul, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A method and semiconductor circuit with which a self-test can be generated and tested with commands by which memory banks are interrogated simultaneously includes a processor for carrying out a built-in self-test and generating commands, each for testing only a respective single memory bank, and an additional processor connected downstream forms more complex multibank commands. Such multibank command formation enables a more diverse test of memories and is carried out faster. Principally, such multibank command generation using a combination of conventional single-bank commands has the advantage of not redeveloping a conventional BIST processor from scratch. It is necessary merely to connect a logic circuit downstream, with which conventional commands are combined, to form the multibank commands. As a result, complex self-test commands that simultaneously access a plurality of memory banks can be generated by a very low development outlay.