Multiple gate transistor employing monocrystalline silicon walls

Abstract

A semiconductor fabrication process and structure in which a dielectric structure ( ) is formed upon a substrate ( ). Silicon is then deposited and processed to form a crystalline silicon wall ( ) that envelopes the dielectric structure ( ) and is physically and electrically isolated from the substrate ( ). A gate dielectric film ( ) is formed over at least two surfaces of the silicon wall ( ) and a gate electrode film ( ) is formed over the gate dielectric ( ). The gate electrode film ( ) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall ( ) disposed on either side of the gate electrode ( ) may then be contacted to form source/drain structures ( ). In this manner, the portion of the silicon wall ( ) covered by the gate electrode ( ) comprises a transistor channel region having multiple surfaces controlled by gate electrode ( ).