Method of scaling table based cell library timing models in order to take into account process, temperature and power supply

Abstract

A method is presented for generating a timing model for a logic cell. Output load indices (Load , Load , . . . ,Load ) are selected which specify output load for the first logic cell. Input ramp indices (IR , IR , . . . ,IR ) are selected which specify input ramp for the first logic cell. Baseline output ramp values (OR [j,k]) are generated for each output load index (Load ) and input ramp index (IR ) pair. In order to take into account process, power and temperature variations, scaling factors are used to scale the indices. For example these scaling factors can be utilized for many different logic cells in a cell library. In one embodiment, the output load indices are scaled by a first scaling factor (&lgr;). The input ramp indices are scaled by a second scaling factor (&rgr;). Scaled output ramp values (OR [j,k]) are generated for each scaled output load index and scaled input ramp index pair. A third scaling factor (&ggr;) is used to generate the scaled output ramp values (OR [j,k]). Additionally, delay values can be generated as well. Specifically, baseline delay values (Delay [j, k]) are generated for each output load index (Load ) and input ramp index (IR ) pair. Scaled delay values (Delay [j, k]) are generated for each scaled output load index and scaled input ramp index pair.