The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2004

Filed:

Mar. 13, 2003
Applicant:
Inventors:

Paul Joseph Kramer, Fort Collins, CO (US);

Jered Michael Sandner, Wellington, CO (US);

Ohad Falik, Kfar Saba, IL;

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G07C 3/00 ;
U.S. Cl.
CPC ...
G07C 3/00 ;
Abstract

A method and apparatus are arranged to provide a multi-bit digital signal that represents a normalized percentage of time that a signal is active. The apparatus includes an N-bit counter that is periodically reset to an initialization condition, and a logic block that processes the output of the N-bit counter. The N-bit counter is arranged to evaluate a monitored signal for each cycle of a clock signal, and modify the count accordingly. The logic block is configured to periodically scan the output of the N-bit counter after the expiration of a sampling time interval. The sampling time interval is determined by a timing circuit such as a window counter that is operated from the clock signal. The logic block periodically evaluates the output of the N-bit counter and provides the normalized multi-bit digital signal.


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