The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2004

Filed:

Sep. 18, 2002
Applicant:
Inventor:

Kazuhide Kurosaki, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

The non-volatile semiconductor memory of the present invention is comprised of: a memory cell array including a plurality of memory cells which is disposed at intersections of a plurality of bit lines and word lines and are connected to said bit lines; and a writing circuit which receives an address signal and supplies a bit line voltage to the bit line connected to the memory cell selected with the address signal during writing operation. The writing circuit changes, based on the address signal, a level of the bit line voltage depending on a position of the selected memory cell in the memory cell array. The writing circuit operates, based on the inputted writing address, to further increase a level of the bit line voltage supplied to the memory cell as the wiring distance via the bit line from the output end of the bit line voltage of the writing circuit thereto is longer, fluctuation of writing speed in each memory cell of a memory cell array is reduced.


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