The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2004

Filed:

Dec. 28, 2001
Applicant:
Inventor:

Gunvant Patel, Garland, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 2/708 ; G01R 1/900 ;
U.S. Cl.
CPC ...
G01R 2/708 ; G01R 1/900 ;
Abstract

The present invention provides for a method ( ) and system ( ) for isolating the input nodes ( ) and/or the output nodes ( ) of an analog device ( ) and performing continuity testing thereof without using relays. The system includes an analog device having a pair of input and output terminals and a plurality of resistors (R -R and R -R ) arranged in parallel and connected thereto. The method for testing continuity of the analog device includes providing a voltage input via at least one of the resistors to either input node, and then measuring the voltage at the same node via a resistor. If a diode drop from ground is sensed there is continuity, and if the applied voltage is sensed at the node there is not continuity. As a result, the invention advantageously isolates the nodes and removes any unwanted capacitance and impedance loading thereon during testing thereof. The invention also allows multiple node testing to be performed simultaneously in parallel, which reduces testing time and permits direct testing on the nodes without the use of external circuit relays.


Find Patent Forward Citations

Patel, Gunvant. (2004). Method and system for conducting continuity testing on analog devices having sensitive input nodes (U.S. Patent No. 6750663). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6750663

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