The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2004

Filed:

Oct. 17, 2000
Applicant:
Inventors:

Kenneth Fallon, Rochester, NY (US);

Miguel A. Jimarez, Newark Valley, NY (US);

Ross W. Keesler, Endicott, NY (US);

John M. Lauffer, Waverly, NY (US);

Roy H. Magnuson, Endicott, NY (US);

Voya R. Markovich, Endwell, NY (US);

Irv Memis, Vestal, NY (US);

Jim P. Paoletti, Endwell, NY (US);

Marybeth Perrino, Apalachin, NY (US);

John A. Welsh, Binghamton, NY (US);

William E. Wilson, Waverly, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01R 1/204 ; H05K 1/11 ;
U.S. Cl.
CPC ...
H01R 1/204 ; H05K 1/11 ;
Abstract

A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.


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