The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2004
Filed:
Jun. 24, 2002
Albrecht Kieslich, Radebeul, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A method of forming a bitline and a bitline contact and a dynamic random access memory (DRAM) cell array includes the following steps. The bitline and the bitline contact are formed in a two-step process, in which, first, the bitline contact is formed in a first dielectric layer and, then, the bitline of a conductive material having a lower resistivity than the bitline contact material is defined in a second dielectric layer ( ). According to a preferred embodiment, the second dielectric layer ( ) is made of a low k dielectric. The retention anneal process, which is usually performed in the standard DRAM process, is preferably made before depositing the bitline material and, optionally, the low k dielectric. A dynamic random access memory cell array having at least one bitline and a bitline contact can be manufactured by this method.