The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2004
Filed:
Aug. 09, 2001
Pawitter Mangat, Gilbert, AZ (US);
Joe Mogab, Austin, TX (US);
Kenneth H. Smith, Chandler, AZ (US);
James R. Wasson, Gilbert, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A stencil mask ( or ) has both a thin membrane layer ( ) and a stress controlled layer ( ) for enabling electron and ion projection lithography at very small geometries. The thin membrane layer ( ) is within a range of substantially forty to two hundred nanometers and is preferably silicon nitride, and the stress controlled layer is preferably a metal or a metal alloy. Annealing of the stress controlled layer ( ) may be performed to obtain a desired stress characteristic. Semiconductors are made using the mask by projecting radiation through the thin membrane stencil mask and reduction optics ( ) onto resist ( ) formed on a plurality of die, the radiation forming a contrast image on the resist that is subsequently developed. Commercially available lithography equipment is compatible with the thin stencil mask.