The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2004
Filed:
Jun. 15, 2000
Charles Roberts Moore, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention is a mechanism for providing redundancy in the register file of a microprocessor such that registers having a defective operational status, as determined by testing, can be tolerated and the baseline specification of the microprocessor can be met. The present invention utilizes the register renaming capability of a microprocessor to allow additional registers, above those called for in the specification to be provided. The registers are then tested and those found “bad” are identified and avoided by the allocation/deallocation logic, which is used to assign registers to the various instructions being executed by the microprocessor. More particularly, the present invention maintains a list of physical registers in a register file that have a functional operational status and are available to be allocated to various instructions as they execute. The allocated registers are typically used to store interim data resulting from the execution of the assigned instruction. When the data in the rename register is complete it is then committed to the architecture by rewriting the results to an architected register. The present invention uses this rename capability to prevent a defective register that was manufactured bad to ever be included in the list of registers that are available for allocation to the processor instructions.