Proprietary core permission structure and method

Abstract

A programmable logic device includes a non-volatile permission memory block to enable a customer to utilize a proprietary core. In one embodiment, the core supplier designs its core to check for a specified permission bit or bit pattern in the permission memory block before the core will operate. If the permission bit or bit pattern is set properly, the core functions correctly when implemented in the PLD. If not, the core will not function. To prevent the customer from modifying the core such that it no longer depends upon the permission bits to function, the configuration bitstream used to program the PLD can be encrypted before and during transmission to the PLD. This encryption ensures security of the customer's logic design as well as the supplier's core design. In this manner, the customer remains dependent upon properly set permission memory bits, i.e. proper authorization, to obtain core functionality.