System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system

Abstract

A system and method for synchronizing the skip pattern to two clock domains and initializing the clock skipping buffer which enables data transfers between the two clock domains. In one embodiment, a circuit comprises a pair of alignment detection units, a synchronous reset unit, a skip pattern generator, a counter reset unit and a data transfer buffer. Each of the alignment units is configured to detect the alignment of the clock signal in one of the clock domains with a reference clock signal and generate a signal indicative of the alignment. This signal is conveyed to the synchronous reset unit and the counter reset unit. The alignment signal generated by one alignment unit is also conveyed to the skip pattern generator. The synchronous reset unit accepts the alignment signals from the alignment units and generates concurrent reset signals (i.e., one for each of the two clock domains) to initialize the counter reset unit. The counter reset unit controls the load and unload counters which control the flow data through the data transfer buffer. After the synchronous reset signals generated by the synchronization reset unit are received, the counter reset unit begins generating load and unload pulses corresponding to the respective clock domains and transmitting these signals to the data transfer buffer.