The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2004
Filed:
Dec. 03, 2002
Aline C. Sadate, Dallas, TX (US);
Wenliang Chen, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A bias generator circuit with improved phase margin without RC compensation includes: a first transistor MP ; a second transistor MP coupled in parallel with the first transistor MP ; an amplifier A having a first input coupled to the first and second transistors MP and MP , and to a gate of the second transistor MP , and a second input coupled to a control voltage node VCTRL; a third transistor MN coupled in series with the first transistor MP ; a fourth transistor MN coupled in series with the third transistor MN and having a gate coupled to an output of the amplifier A ; a fifth transistor MP ; a sixth transistor MP coupled in parallel with the fifth transistor MP ; a seventh transistor MN coupled in series with the fifth transistor MP ; and an eighth transistor MN coupled in series with the seventh transistor MN and having a gate coupled to a gate of the fourth transistor MN . In order to maintain the bias generator stability for different biasing conditions, the feed-forward path is removed by diode connecting the second transistor MP instead of connecting the gate of the second transistor MP to the control voltage node VCTRL.